1. Field of the Invention
The present invention relates to semiconductor memory devices, particularly to a dynamic semiconductor memory device with a sense amplifier circuit that differentially amplifies data in memory cells. More particularly, the present invention relates to a structure of a sense power supply circuit generating a power supply voltage of a sense amplifier circuit.
2. Description of the Background Art
In accordance with the development of recent computers and information processing terminals, the demand placed on devices employed as the main storage in these equipment has become higher. More specifically, there is an increasing not only for large storage capacity, but also for increasing the effective data transfer rate and lowering power consumption to allow usage of a large storage capacity memory in portable apparatuses. As to a DRAM (dynamic random access memory) widely used as the main memory device, a SDRAM that carries out data input/output in synchronization with clock signals (clock synchronous type DRAM), a DDR (double data rate) SDRAM that carries out data input/output in synchronization with both the rising and falling edges of clock signals, and the like, typical of a DRAM that allows data to be transferred at high speed, are beginning to be employed widely.
In a DRAM, information is stored in the form of electrical charges in a capacitor of a memory cell. Since data of a H (high) level written into a DRAM cell will be naturally lost by leakage current when left intact, a data re-write operation called "refresh" must be carried out periodically.
In recent DRAMs, an operation called self refresh is defined by specification. In a self refresh operation mode, a refresh timing is set automatically by a timer provided in the DRAM. A refresh operation is carried out automatically at the set refresh timing. The self refresh operation is carried out during a standby state in which the DRAM is not accessed. By suppressing the self refresh current consumed during this self refresh operation, the current consumption of the DRAM can be reduced to increase the continuous operative period of time of, for example, portable communication information terminals (by virtue of increase of the battery lifetime).
The basic factors determining the value of the self refresh current depend on the bit line potential amplitude, the bit line load and the refresh cycle. The refresh cycle is closely related to the data retaining ability of the memory cell. A longer refresh cycle can be set as the data retaining ability of the memory cell becomes higher. As a method of increasing the memory cell data retaining ability on a circuit basis, Asakura et al. has proposed the BSG (boosted sense ground) scheme. This BSG scheme is described in details in, for example, IEEE Journal of Solid-State Circuits 1994, pp.1303-1309. The principle of the BSG scheme will described in the following.
FIG. 35 represents a structure of a memory cell array in a DRAM with the conventional BSG scheme. Referring to FIG. 35, the DRAM includes memory cells MC arranged in a matrix of rows and columns, a pair of bit lines BL and ZBL arranged corresponding to each column, and a word line WL arranged corresponding to each row of memory cells MC. In FIG. 35, one memory cell MC is depicted as a representative. Memory cell MC includes a memory cell capacitor Cs to store information, and an access transistor MT formed of an N channel MOS transistor (insulation gate field effect transistor) and rendered conductive in response to a signal voltage on word line WL to connect memory cell capacitor Cs to bit line BL. Each of bit lines BL and ZBL has a parasitic capacitance (bit line capacitance) Cb.
Bit lines BL and ZBL are provided with a bit line equalize/precharge circuit E/P precharging and equalizing bit lines BL and ZBL to an intermediate voltage Vble in response to a bit line equalize designation signal BLEQ, and a sense amplifier circuit S/A amplifying the voltage difference of bit lines BL and ZBL in response to sense amplifier activation signals SON and ZSOP.
Bit line equalize/precharge circuit E/P includes precharge transistors TQ7 and TQ8 transmitting intermediate voltage Vble to respective bit lines BL and ZBL in response to bit line equalize designation signal BLEQ, and an equalize transistor TQ9 electrically short-circuiting bit lines BL and /BL in response to bit line equalize designation signal BLEQ. Transistors TQ7-TQ9 are formed of N channel MOS transistors. Intermediate voltage Vble is equal to the voltage level of the intermediate value between a sense power supply voltage Vdds and a voltage Vbsg higher than ground voltage GND, i.e. (Vdds+Vbsg)/2.
Sense amplifier circuit S/A includes an N sense amplifier rendered active, when sense amplifier activation signal SON is active, to discharge one of bit lines BL and /BL of the lower potential, and a P sense amplifier rendered active, when sense amplifier activation signal ZSOP is active, to charge another of bit lines BL and /BL of the higher potential. The N sense amplifier includes: an N channel MOS transistor TQ1 having a drain connected to bit line BL and a gate connected to bit line /BL, an N channel MOS transistor TQ2 having a drain connected to bit line /BL and a gate connected to bit line BL, and an N channel MOS transistor TQ3 rendered conductive, when sense amplifier activation signal SON is active, to transmit sense power source voltage Vsan (=Vbsg) to the sources of MOS transistors TQ1 and TQ2. In the BSG scheme, sense power source voltage Vsan is set to the level of a boosted voltage Vbsg higher than ground voltage GND.
The P sense amplifier includes a P channel MOS transistor TQ4 having a drain connected to bit line BL and a gate connected to bit line /BL, a P channel MOS transistor TQ5 having a drain connected to bit line /BL and a gate connected to bit line BL, and a P channel MOS transistor TQ6 rendered conductive when sense amplifier activation signal ZSOP is active to transmit sense power supply voltage Vsap to the sources of MOS transistors TQ4 and TQ5. Sense power supply voltage Vsap corresponds to the level of sense power supply voltage Vdds. The refresh operation of memory cell MC will now be described with reference to the signal waveform diagram of FIG. 36.
In a standby state, sense amplifier activation signal SON is at an L level of ground voltage GND, and sense amplifier activation signal ZSOP is at an H level of sense power supply voltage Vdds. Sense amplifier circuit S/A is in an inactive state. Bit line equalize designation signal BLEQ is at an active state of an H level. MOS transistors TQ7-TQ9 included in bit line equalize/precharge circuit E/P all stay in a conductive state. Bit lines BL and /BL are precharged and equalized to the level of intermediate voltage Vble. Word line WL is at the level of ground voltage GND. Access transistor MT of memory cell MC maintains a non-conductive state.
Upon access to a memory cell (starting of a refresh cycle), bit line equalize designation signal BLEQ is pulled down to an L level. Bit line equalize/precharge circuit E/P is rendered inactive. Bit lines BL and ZBL attain a floating state at the level of intermediate voltage Vble.
By a row select circuit not shown, word line WL is driven to a selected state according to an address signal, whereby the voltage level of word line WL rises. When the voltage level of word line WL becomes higher than the voltage level of bit line BL by the threshold voltage of the access transistor, access transistor MT is rendered conductive, whereby charge is transferred between bit line BL and memory cell capacitor Cs. FIG. 36 represents an operation waveform when memory cell MC stores data of an H level, and the voltage level of bit line BL rises.
Since bit line ZBL does not have a memory cell connected thereto, bit line ZBL maintains the level of intermediate voltage Vble.
When the voltage difference between bit lines BL and ZBL becomes large enough, sense amplifier activation signals SON and ZSOP are rendered active. In response to sense amplifier activation signal SON attaining an H level of an active state, MOS transistor TQ3 in sense amplifier circuit S/A conducts. Sense power source voltage Vsan is transmitted to the sources of MOS transistors TQ1 and TQ2. The N sense amplifier is rendered active, and bit line ZBL of the lower potential is discharged to the level of sense power source voltage Vsan (=Vbsg). In the case sense amplifier activation signal ZSOP is rendered active to attain an L level, MOS transistor TQ6 in sense amplifier circuit S/A is rendered conductive. Sense power supply voltage Vsap is transmitted to the sources of MOS transistors TQ4 and TQ5. The P sense amplifier is rendered active. By this P sense amplifier, bit line BL of the higher potential is charged to the level of sense power supply voltage Vsap (=Vdds).
Word line WL is at the level of high voltage Vpp higher than sense power supply voltage Vdds. Therefore, the H level data corresponding to the level of sense power supply voltage Vdds on bit line BL is transmitted to memory cell capacitor Cs impervious to the loss of the threshold voltage at access transistor MT. Thus, the H level data rewrite and refresh operation of memory cell MC is completed. In the case where memory cell MC stores data of an L level, a similar refresh operation is carried out in which a voltage of a level corresponding to sense power source voltage Vsan (=Vbsg) is transmitted to memory cell capacitor Cs. As to the voltage level of the data stored in a memory cell, the voltage level of H data is equal to the level of sense power supply voltage Vdds, whereas the voltage level of L data is equal to the voltage level of sense power source voltage Vsan (Vbsg).
When the refresh cycle is completed, word line WL is driven to a non-selected state. Then, sense amplifier activation signals SON and ZSOP are rendered inactive sequentially. As a result, the refreshed data is stored in memory cell MC. Then, bit line equalize designation signal BLEQ is rendered active at an H level, whereby bit line equalize/precharge circuit E/P becomes active. Bit line BL and ZBL are precharged and equalized to the level of intermediate voltage Vble.
In the BSG scheme, sense power source voltage Vsan is set to the level of a voltage Vbsg that is higher than ground voltage GND. The advantage of setting sense power source voltage Vsan to a level higher than ground voltage GND in the BSG scheme will be described briefly in the following.
FIG. 37 schematically shows a structure of a cross section of memory cell MC. Referring to FIG. 37, memory cell MC includes N type impurity regions 502a and 502b of high concentration formed spaced apart at the surface of a semiconductor substrate, a conductive layer 504 formed on a channel region between impurity regions 502a and 502b with a gate insulation film 503 laid thereunder, and a conductive layer 505 electrically connected to impurity region 502a. Two layers of interlayer insulation films 506a and 506b are formed on conductive layers 504 and 505. Conductive layer 504 corresponds to word line WL, whereas conductive layer 505 corresponds to bit line BL.
Memory cell MC further includes a conductive layer 510 electrically connected to impurity region 502b via a contact hole formed in interlayer insulation films 506a and 506b, and a conductive layer 514 laid above conductive layer 510. Conductive layer 510 is formed so that the cross section of the upper portion has a U shape. Conductive layer 514 includes a protrusion 514a extending into the U shape via capacitor insulation film 512 at a region above conductive layer 510. Conductive layer 510 functions as a connection node connecting access transistor MT and memory cell capacitor Cs, i.e. a storage node SN. Memory cell capacitor Cs is formed at a region where conductive layer 510 faces conductive layer 514 via capacitor insulation film 512.
Although memory cell MC has a stacked capacitor structure in FIG. 37, this stacked capacitor may have another structure such as a cylindrical shape, fin shape, cross sectional T shape structures, or the like.
Consider the state where word line WL is held at the level of ground voltage GND, intermediate voltage Vble is applied to bit line BL, and storage node SN retains a voltage Vch corresponding to an H level data in memory cell MC of FIG. 37. A cell plate voltage Vcp (Vbsg+Vdds)/2) is applied to conductive layer 514 functioning as a cell plate electrode layer CP.
The main leakage sources in memory cell MC are (1) a leakage current Ils flowing towards a P substrate 500 via the PN junction between impurity region 502b of memory cell capacitor Cs and P type substrate (P type semiconductor substrate) 500, and (2) a leakage current Ilb towards bit line BL determined by the sub threshold characteristic of the access transistor.
The magnitude of leakage current Ils towards P type substrate 500 depends upon a voltage difference Vpn applied across the PN junction between impurity region 502b and P type substrate 500. The leakage current Ils becomes greater as voltage difference Vpn becomes larger. In FIG. 37, the voltage of storage node SN is a voltage Vch corresponding to H level data. Since bias voltage Vbb is applied to P type substrate 500, voltage difference Vpn is represented by the following equation. EQU Vpn=Vch-Vbb
Leakage current Ilb flowing towards bit line BL via the access transistor is represented by the following equation according to the difference between gate-source voltage Vgs and threshold voltage Vth of the access transistor. EQU Ilb=Ilb0.multidot.10 (Vgs-Vth)/S (1)
where " " represents the exponentiation. In equation (1), Ilb0 is the current value defining threshold voltage Vth, and S is a coefficient determined depending upon the transistor structure and process, represented by dVgs/d log Id. Here, Id represents a drain current. PA1 (a) As shown in FIG. 38B, back gate bias voltage (bias voltage Vbb of the P type substrate) is set to the level of ground voltage GND, whereas a positive voltage Vbsg is applied, as a voltage corresponding to L level data, to bit line BL (or ZBL). Word line WL is at the level of ground voltage GND when kept in a non-selected state. Therefore, gate-source voltage Vgs of access transistor MT becomes a negative voltage of -Vbsg. PA1 (b) Since ground voltage GND is applied to P type substrate 500, voltage difference Vpn applied across the PN junction between impurity region 502b and P type substrate 500 at storage node SN becomes equal to voltage Vch of H level data. The voltage difference applied across the PN junction of the storage node can be reduced by the change of the substrate voltage from the negative voltage to the ground voltage. In response, substrate leakage current Ils flowing via the PN junction of storage node SN can be reduced. PA1 (c) The precharge voltage of bit line BL must be 1/2 times the bit line potential amplitude. Therefore, bit line precharge voltage (intermediate voltage) Vble becomes Vdds/2+Vbsg/2, as shown in FIG. 36. Since this precharge voltage is charged up to the level of sense power supply voltage Vdds, bit line amplitude dVbl can be reduced by Vbsg/2 in comparison to the structure where the bit line is driven to the level of ground voltage GND.
In equation (1), it seems that leakage current Ilb does not depend upon voltage Vbl of bit line BL to which the access transistor is connected. However, threshold voltage Vth depends upon the substrate-source voltage of Vbs=Vbb-Vbl. Therefore, the absolute value of substrate-source voltage Vbs becomes smaller as the bit line voltage, i.e., source voltage Vbl is lower to result in a smaller threshold voltage Vth.
For example, in the case where a corresponding bit line BL of the memory cell connected to a non-selected word line is at a voltage level corresponding to L level data (in the conventional case, bit line voltage Vbl is equal to ground voltage GND) in the memory block to be refreshed, the access transistor of the memory cell connected to this non-selected word line has a smaller absolute value of substrate-source voltage Vbs even if word line WL is at the level of ground voltage GND. Therefore, bit line leakage current Ilb becomes greater. As appreciated from equation (1), even if threshold voltage Vth slightly varies by 0.1 V, bit line leakage current Ilb varies approximately ten times as large since the S factor is approximately 0.1 V.
In order to suppress bit line leakage current Ilb, the approach of setting the substrate bias voltage Vbb applied to P type substrate 500 to a negative voltage can be considered as shown in FIG. 38A. By setting substrate bias voltage Vbb to a deep bias voltage in the negative direction, the absolute value of the substrate-source voltage Vbs can be increased, which in turn allows a larger threshold voltage Vth to suppress bit line leakage current Ilb. However, the voltage difference Vpn applied across the PN junction between impurity region 502b and P type substrate 500 becomes greater to increase substrate leakage current Ils. Sense power supply voltage Vdds determines the level of voltage Vch corresponding to H level data of storage node SN. If sense power supply voltage Vdds is reduced where substrate leakage current Ils increases by this substrate bias deep in the negative direction, it will become difficult to retain the H level data for a long period of time. The BSG scheme provides the following advantages.
In other words, gate-source voltage Vgs of access transistor MT can be set negative even if a negative voltage is not applied to P type substrate 500. Also, the voltage Vbs applied to the PN junction between source impurity region 502a of access transistor MT and P type substrate 500 of this access transistor MT can be kept negative without negative substrate voltage Vbb. As a result, negative value of Vgs and Vbs suppresses the leakage current Ilb.
By the above (a) and (b), the refresh interval can be set longer since the speed of losing H level data is alleviated. In addition, by the above (c), current consumption during sense operation can be reduced.
Thus, the BSG scheme has the advantage of reducing the sense current and improving the refresh characteristics. Bias voltage Vbb applied to the substrate region of the access transistor, i.e. to the back gate thereof is equal to ground voltage GND. It is not necessary to apply a negative bias voltage, so that the circuit configuration can be simplified. However, the L level voltage (=Vbsg) of the bit line BL is higher than ground voltage GND by approximately 0.4-0.5 V. The bit line precharged to the level of the intermediate voltage must be discharged and is held at the level of voltage Vbsg. If a diode-connected P-channel MOS transistor is employed for generating such a low level positive voltage as the sense boosted sense ground voltage, it is difficult to generate a stable bit line boosted sense ground voltage Vbsg due to a disadvantageous factor of the P-MOS transistor, such as variation in threshold voltage and temperature dependency.
A large bit line discharging current will be conducted immediately after the sense amplifier circuit is rendered active and a sensing operation is started. In order to suppress the influence by this bit line discharging current to prevent transient variation of the boosted sense ground voltage Vbsg, an extremely high current drivability and also the ability to maintain the voltage level stably are required for the circuit that generates the boosted sense ground voltage Vbsg. Therefore, the BSG scheme has the technical subject of generating and supplying a boosted sense ground voltage Vbsg always stably as a sense ground voltage, covering the transient variation problem.
To solve such problems in the BSG scheme, Kono et al. propose a novel sense scheme of "A Precharged-Capacitor-Assisted Sensing (PCAS) Scheme with Novel Level Controller for Low Power DRAMs" in 1999 Symposium on VLSI Circuits, Digest of Technical Papers, pp.123-124. This PCAS scheme generates a boosted sense ground voltage Vbsg at an accurate voltage level on bit line BL or ZBL by precharging the decouple capacitance in advance in accordance with the bit line charging/discharging charge that is required in a sensing operation, followed by coupling the decouple capacitance with the sense power supply line/sense ground line in the sense amplifier circuit operation mode. Reduction of the absolute value of gate-source voltage Vgs of the MOS transistor in the sense amplifier circuit caused by voltage variation in the sense power supply line/sense ground line can be prevented to speed up the sensing operation.
It is to be noted that variation of the level of boosted sense ground voltage Vbsg occurs, not only in the sense period where the sense amplifier circuit operates, but also in the period when the sense amplifier circuit corresponding to the selected column is coupled to an internal data line. More specifically, the internal data line pair is generally precharged to an H level, so that charge flows into the sense amplifier circuit and the bit line pair by the precharge voltage of the internal data line when they are coupled. As a result, the level of boosted sense ground voltage Vbsg changes.
In the case of the above PCAS scheme, booted sense ground voltage Vbsg can be accurately generated after the period of the sensing operation. As to stabilization of boosted sense ground voltage Vbsg in writing/reading data, voltage variation on the sense power supply line and sense ground line can be suppressed to some extent since the decouple capacitance is coupled to the sense power supply line/sense ground line during the activation period of the sense amplifier circuit. However, no particular consideration was made as to effective measures to stabilize the level of the boosted sense ground voltage in the writing/reading operation of data.
Particularly in the case where the level of boosted sense ground voltage Vbsg is increased in a data writing/reading operation mode, there is a possibility of degrading the stability of the sense amplifier circuit. There is also the possibility of causing a failure such as erroneous data readout since the L level data read out margin is lost due to increase of the voltage level of the L level data of a selected memory cell.